This invention relates generally to processing within a computing environment, and more particularly to determining the refreshing eDRAM in a high performance cache architecture.
Every new generation of high performance computers seeks increases in performance. There are several methods employed to increase performance, one such method is to increase the size of the computer processor memory caches. Computer processor memory caches are used to improve the access speed of data by storing more frequently used data in fast memory located as close as possible to the computer processor. These computer processor memory caches can include Static Random Access Memory (SRAM) circuits for example. Higher performance computer systems, however, use Embedded Dynamic Random Access Memory (eDRAM) cache circuits. The eDRAM cache is allows for greater capacity in a smaller area by including a higher density of memory circuits within the same area. The eDRAM cache also provides higher performance as compared to SRAM cache. eDRAM cache, however, requires periodic refreshing of the contents of memory. These periodic refreshes may result in degraded performance.